The JTAGMaster Tester and Programmer is a fully integrated solution for the configuration and diagnosis of Programmable Logic Devices (PLDs). This unit includes :
A boundary-scan tester to arbitrarily observe individual pins and therefore determine their functionality. This information can be saved in customisable test procedures which can also include pictures and datasheets. EXTEST mode is also available to manually change the state of pins and trace the effect(s) on the other device(s) in the chain. Scan Check is a multi-license software to run boundary scan checks on multiple stations.
A programming interface designed to handle industry standard JAM STAPL files (Standard Test And Programming Language) and SVF files (Serial Vector Format) to send programming instructions as well as testing functions to the device. ABI uses the JTAG Standards (Joint Test Action Group, compatible with IEEE1149.1) which ensures compatibility between all compliant ICs.
The JTAGMaster is also capable of programming EEPROM devices using external adapters. Standard brinary files are supported and can also be modified in the device buffer window. A wide range of EEPROM devices are present in the library which can be easily modified by users. The following protocols are supported by the JTAGMaster :